Appendix A: Glossary of Acronyms

As with any specialized engineering discipline, the world of Cyber-Physical Systems and computer architecture is drowning in acronyms. Below is a comprehensive reference guide to the abbreviations used throughout this book, translating the alphabet soup back into plain English.

• AAL (Actuator Abstraction Layer): A software boundary that isolates high-level control algorithms (like a PID loop) from the physical limitations and saturation points of the hardware actuators.
• ADC (Analog-to-Digital Converter): A hardware peripheral that samples continuous physical voltages and quantizes them into discrete integer values for the CPU.
• AXI (Advanced eXtensible Interface): A high-performance, multi-channel AMBA interconnect protocol designed by ARM that uses a VALID/READY handshake to pipeline transactions across an SoC.
• CAN (Controller Area Network): A legacy, unencrypted, serial communication bus standard used extensively in automotive and industrial networks.
• CPS (Cyber-Physical System): An engineered system that seamlessly integrates computational algorithms, networking, and physical processes.
• CPTI (Cyber-Physical Threat Intelligence): An integrated security approach that models cyber and physical events holistically to understand how digital attacks (like false data injection) create physical kinetic impacts.
• DER (Distributed Energy Resource): Small, decentralized energy generation and storage assets, such as rooftop solar panels and electric vehicle batteries.
• DMA (Direct Memory Access): A specialized hardware co-processor that moves blocks of data between memory and peripherals without burning CPU instruction cycles.
• DSA (Domain-Specific Architecture): Custom silicon tailored to execute a very narrow set of computational tasks (such as AI matrix multiplication) with massive energy efficiency, completely sacrificing the flexibility of a general-purpose CPU.
• ECU (Electronic Control Unit): An embedded microcontroller system found inside vehicles responsible for managing specific subsystems like engine timing, braking, or infotainment.
• FL (Federated Learning): A decentralized machine learning technique where the global model is sent to the edge nodes for local training, rather than sending raw, private sensor data to the cloud.
• FOTA (Firmware Over-The-Air): The process of wirelessly patching or upgrading the firmware of a remote device, utilizing A/B partitioning and hardware watchdogs to prevent bricking during a failed update.
• HBM (High Bandwidth Memory): An advanced memory architecture that vertically stacks multiple DRAM dies on top of a logic base and connects them via Through-Silicon Vias (TSVs) to deliver terabytes-per-second bandwidth to GPUs and TPUs.
• HSM (Hardware Security Module): An isolated, tamper-resistant cryptographic co-processor used to safely store private keys and execute secure boot verifications.
• I2C (Inter-Integrated Circuit): A half-duplex, two-wire (SCL/SDA) serial protocol that uses open-drain pins and device addresses to allow multiple chips to communicate on a shared bus.
• ISA (Instruction Set Architecture): The boundary between software and hardware; the specific set of machine instructions, registers, and memory models that a processor understands.
• ISR (Interrupt Service Routine): A dedicated software function that the CPU vectors to immediately upon receiving a hardware interrupt.
• LLM (Large Language Model): A massive neural network based on the Transformer architecture (e.g., GPT-4) that relies on billions of parameters and consumes datacenter-scale computing resources.
• LR (Link Register): A dedicated CPU register (like X30 in AArch64 or x1 in RISC-V) that stores the return address during a function call, avoiding the latency of pushing the address to memory.
• MAC (Multiply-Accumulate): The foundational arithmetic operation of digital signal processing and neural networks, combining a multiplication and an addition into a single step.
• MMIO (Memory-Mapped I/O): An architectural design where peripheral control registers are accessed by the CPU using standard memory load and store instructions to specific physical addresses.
• NVIC (Nested Vectored Interrupt Controller): An advanced hardware block integrated tightly with ARM Cortex-M cores that autonomously handles interrupt prioritization, preemption, and context saving.
• PID (Proportional-Integral-Derivative): A continuous feedback control loop algorithm that computes corrective actions based on the present error, the accumulation of past errors, and the predicted future rate of error.
• PIP (Priority Inheritance Protocol): An RTOS kernel mechanism that temporarily elevates the priority of a low-priority task holding a mutex to prevent priority inversion and unbounded delays.
• PWM (Pulse-Width Modulation): A digital technique used to approximate an analog output by rapidly switching a signal high and low at varying duty cycles.
• RMS (Rate Monotonic Scheduling): A static-priority RTOS scheduling algorithm where tasks with shorter execution deadlines are mathematically assigned higher priorities.
• RTOS (Real-Time Operating System): A specialized operating system kernel designed to guarantee deterministic, hard deadlines for task execution and context switching.
• SAL (Sensor Abstraction Layer): A software barrier that filters noise and quantization errors out of raw analog hardware readings before they are fed into continuous-time physics equations.
• SDN (Software-Defined Networking): A network architecture that removes routing logic from physical switches and centralizes it in a programmable software controller to guarantee deterministic Quality of Service (QoS).
• SIMD (Single Instruction, Multiple Data): An architectural execution model where a single machine instruction applies the exact same operation to multiple data elements simultaneously (e.g., ARM NEON).
• SP (Stack Pointer): A dedicated CPU register used to track the current top of the call stack in memory.
• TCB (Task Control Block): A data structure maintained by an RTOS in RAM that holds the identity, state, priority, and saved stack pointer of a specific thread.
• TLB (Translation Lookaside Buffer): A highly specialized, fast hardware cache inside the Memory Management Unit (MMU) that stores recent virtual-to-physical page address translations.
• TPM (Trusted Platform Module): A secure hardware trust anchor that ensures system integrity, generates true random numbers, and securely locks cryptographic keys.
• TPU (Tensor Processing Unit): A custom Domain-Specific Architecture created by Google that uses massive 2D systolic arrays to accelerate deep neural network training and inference.
• UART (Universal Asynchronous Receiver-Transmitter): A hardware peripheral that transmits and receives serial data asynchronously over independent TX and RX wires, framed by start and stop bits.
• VPP (Virtual Power Plant): A decentralized network of distributed energy resources (like home batteries and solar panels) aggregated and orchestrated by software to behave like a traditional power plant.
• WSC (Warehouse-Scale Computer): A datacenter where tens of thousands of servers, storage arrays, and network switches are architected and managed as a single, massive, utility-computing machine.